منو
علی جهانیان

دانشیار

تاریخ به‌روزرسانی: 1403/02/12

علی جهانیان

مهندسی و علوم کامپیوتر / معماری کامپیوتر و شبکه

مقالات علمی چاپ شده در مجلات

  1. "Systematic Trojan Detection in Crypto-Systems using the Model Checker"
    Hamed Hossein talaee, Ali Jahanian
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, Vol. 3, pp.1-20, 2024
  2. "Cross-Device Deep Learning Side-Channel Attacks using Filter and Autoencoder"
    Maryam Sadat Tabaeifard, Ali Jahanian
    ISeCure-ISC International Journal of Information Security, Vol. 23, pp.149-158, 2023
  3. "RTL2DNA: an Automatic Flow of Large-Scale DNA-based Logic Circuit Design"
    Zohreh Beiki, Ali Jahanian
    Scientia Iranica, pp.1-25, 2022
  4. "Generic and Scalable DNA-based Logic Design Methodology for Massive Parallel Computation"
    Zohreh Beiki, Ali Jahanian
    JOURNAL OF SUPERCOMPUTING, Vol. 79, pp.1426-1450, 2022
  5. "A Time Randomization based Countermeasure against the Template Side Channel Attack"
    Farshideh Kordi, Hamed Hossein talaee, Ali Jahanian
    ISeCure-ISC International Journal of Information Security, Vol. 14, pp.47-55, 2022
  6. "Multi-input DNA-based Logic Gates for Profiling the microRNA Biomarkers of Hepatitis-C Viral Infection"
    Melika sadat Masoud, Mercedeh Sanjabi, Ali Jahanian
    Journal on Computer Science and Engineering, Vol. 18, pp.16-23, 2021
  7. "Power side-channel leakage assessment and locating the exact sources of leakage at the early stages of ASIC design process"
    Vahhab Samadi Bokharaie, Ali Jahanian
    JOURNAL OF SUPERCOMPUTING, Vol. 113, pp.2219-2244, 2021
  8. "Analytical design of multi-threshold and high fan-in DNA-based logical sensors to profile the pattern of MS microRNAs"
    Mercedeh Sanjabi, Ali Jahanian
    Biomedical Engineering Letters, Vol. 11, pp.131-145, 2021
  9. "Intensive Analysis of Physical Parameters of Power Sensors for Remote Side-Channel Attacks"
    Milad Salimian, Ali Jahanian
    ISeCure-ISC International Journal of Information Security, Vol. 13, pp.163-176, 2021
  10. "Side-channel leakage assessment metrics and methodologies at design cycle: A case study for a cryptosystem"
    Vahhab Samadi Bokharaie, Ali Jahanian
    Journal of Information Security and Applications, Vol. 54, 2020
  11. "RNA Secondary Structured Logic Gates for Profiling the microRNA Cancer Biomarkers"
    Mahsa Yazdani, Zohreh Beiki, Ali Jahanian
    IET Nanobiotechnology, Vol. 14, pp.181-190, 2019
  12. "Multi-threshold and Multi-input DNA Logic Design Style for Profiling the MicroRNA Biomarkers of Real Cancers"
    Mercedeh Sanjabi, Ali Jahanian
    IET Nanobiotechnology, Vol. 13, pp.665-673, 2019
  13. "A Customized Digital Microfluidic Biochip Architecture/CAD flow for Drug Discovery Applications"
    Shadi Momtahen, Taajobian Maryam, Ali Jahanian
    IEEE Nanotechnology Magazine, Vol. 13, pp.25-34, 2019
  14. "Drug Discovery Acceleration using Digital Microfluidic Biochip Architecture and computer-aided-design flow"
    Shadi Momtahen, Taajobian Maryam, Ali Jahanian
    International Journal of Engineering, Vol. 32, pp.1169-1176, 2019
  15. "Real Parallel and Constant Delay Logic Circuit Design Methodology based on the DNA Model-of-Computation"
    Zohreh Beiki, Zahra Zare Dorabi, Ali Jahanian
    MICROPROCESSORS AND MICROSYSTEMS, Vol. 61, pp.217-226, 2018
  16. "Massive Parallel Digital Micrflouidic Biochip Architecture for Automating Large-Scale Biochemistry Assays"
    Abbas Haddad, Maryam Taajobian, Ali Jahanian
    Scientia Iranica, Vol. 25, pp.3461-3474, 2018
  17. "DENA A Configurable Micro-architecture and Design Flow for Bio-medical DNA-based Logic Design"
    Zohreh Beiki, Ali Jahanian
    IEEE Transactions on Biomedical Circuits and Systems, Vol. 11, pp.1077-1086, 2017
  18. "Three-dimensional Physical Design Flow for Monolithic 3D-FPGAs to Improve Timing Closure and Chip Area Systems"
    Armin Belghadr, Ali Jahanian
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, Vol. 26, 2017
  19. "Customized Placement Algorithm of Nanoscale DNA Logic Circuits"
    Sedighe Farhadtoosky, Ali Jahanian
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, Vol. 26, 2017
  20. "Improved Experimental Time of Ultra large Bioassays using a Parallelized Microfluidic Biochip Architecture/Scheduling"
    Maryam Taajoban, Ali Jahanian
    IET Nanobiotechnology, Vol. 4, pp.484-490, 2017
  21. "Higher Security of ASIC Fabrication Process Against Reverse Engineering Attack using Automatic Netlist Encryption Methodology"
    SHARAREH ZAMANZADEH, Ali Jahanian
    MICROPROCESSORS AND MICROSYSTEMS, Vol. 42, pp.1-9, 2016
  22. "Higher Flexibililty of Reconfigurable Digital Micro/Nano Fluidic Biochips using an FPGA-Inspired Architecture"
    , Ali Jahanian
    Scientia Iranica, Vol. 23, pp.1554-1562, 2016
  23. "Self Authentication Path Insertion in FPGA-based Design Flow for Tamper-resistant Purpose"
    SHARAREH ZAMANZADEH, Ali Jahanian
    ISeCure-ISC International Journal of Information Security, Vol. 8, pp.53-60, 2016
  24. "Security Path an Emerging Design Methodology to Protect the FPGA IPs against Passive/Active Design Tampering"
    SHARAREH ZAMANZADEH, Ali Jahanian
    JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, Vol. 32, pp.329-343, 2016
  25. "ASIC Design Protection against Reverse Engineering during the Fabrication Process using Automatic Netlist Obfuscation Design Flow"
    SHARAREH ZAMANZADEH, Ali Jahanian
    ISeCure-ISC International Journal of Information Security, Vol. 8, pp.87-98, 2016
  26. "Security-aware Register Placement to Hinder Malicious Hardware Updating and Improve Trojan Detectability"
    , Ali Jahanian
    isesco journal of science and technology, Vol. 7, pp.1-7, 2015
  27. "Three-dimensional Switchbox Multiplexing in Emerging 3D-FPGAs to Reduce Chip Footprint and Improve TSV Usage"
    Marzieh Morshedzadeh, Ali Jahanian, Payam Poor Ashraf
    INTEGRATION-THE VLSI JOURNAL, Vol. 50, pp.81-90, 2015
  28. "Redesigned CMOS (4 2) compressor for fast binary multipliers"
    , Ghassem Jaberipur, Ali Jahanian
    CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE, Vol. 36, pp.111-115, 2014
  29. "Metro-on-FPGA a feasible solution to improve the congestion and routing resource management in future FPGAs"
    Armin Belghadr, Ali Jahanian
    INTEGRATION-THE VLSI JOURNAL, Vol. 47, pp.96-104, 2014
  30. "Improved Delay and Process Variation Tolerance of Clock Tree Network in Ultra-large Circuits using Hybrid RF/Metal Clock Routing"
    , Ali Jahanian
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, Vol. 23, pp.1-19, 2014
  31. "High Performance CMOS (4 2) Compressors"
    Abdoreza Pishvaie, Ghassem Jaberipur, Ali Jahanian
    INTERNATIONAL JOURNAL OF ELECTRONICS, Vol. 101, pp.1511-1525, 2014
  32. "High Performance CMOS (4 2) compressor"
    , Ghassem Jaberipur, Ali Jahanian
    Taylor Francis, 2014
  33. "A Fast Placement Algorithm for Embedded Just-In-Time Reconfigurable Extensible Processing Platform"
    Seyedhassan Daryanavard, Mohammad Eshghi, Ali Jahanian
    JOURNAL OF SUPERCOMPUTING, Vol. 71, pp.121-143, 2014
  34. "Improved CMOS (4 2) compressor designs for parallel multipliers"
    , Ghassem Jaberipur, Ali Jahanian
    COMPUTERS and ELECTRICAL ENGINEERING, Vol. 38, pp.1703-1716, 2012
  35. "Improved Line Tracking System for Autonomous Navigation of"
    Yahya Zare Khafri, Ali Jahanian
    INTERNATIONAL JOURNAL OF ROBOTICS and AUTOMATION, Vol. 30, pp.25-30, 2012
  36. "Improved Timing Closure by Analytical Buffer and TSV Planning in Three-dimensional Chips"
    Ali Jahanian, rEZA Abdollahi
    IEICE ELECTRONICS EXPRESS (MSRT BLACKLIST), Vol. 9, pp.1849-1854, 2012
  37. "Performance Improvement and Congestion Reduction of Large FPGAs using On-chip Microwave Interconnects"
    Armin Belghadr, Ali Jahanian
    IEICE TRANSACTIONS ON COMMUNICATIONS, Vol. 95, pp.1610-1618, 2012
  38. "Trojan Vulnerability Map an Efficient Metric for Modeling and Improvement of Hardware Security Level"
    Abdolmahmood Bakhshizadeh, Ali Jahanian
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, Vol. 95, pp.1-9, 2012
  39. "Parallelizing the FPGA Global Routing Algorithm on Multi-core Systems without Quality Degradation"
    , Ali Jahanian
    IEICE ELECTRONICS EXPRESS (MSRT BLACKLIST), Vol. 24, pp.2061-2067, 2011
  40. "Improved predictability timing yield and power consumption using hierarchical highways-on-chip planning methodology"
    Ali Jahanian, Morteza Saheb zamani, Hamid Safizadeh
    INTEGRATION-THE VLSI JOURNAL, Vol. 44, pp.123-135, 2011
  41. "Comparative Performance Evaluation of Large FPGAs with CNFET- and CMOS-based Switches in Nanoscale"
    , Ali Jahanian, - -
    JOURNAL NANO MICRO LETTERS, Vol. 3, pp.177-178, 2011
  42. "Comparative Performance Evaluation of Large FPGAs with CNFET- and CMOS based Switches in Nanoscale"
    , Ali Jahanian, Keyvan Navi
    JOURNAL NANO MICRO LETTERS, Vol. 3, 2011
  43. "Using chip master planning in automatic ASIC design flow to improve performance and buffer resource management"
    Ali Jahanian,
    Journal of computer and robotics, pp.125-135, 2011
  44. "Comparative Performance Evaluation of Large FPGAs with CNFET and CMOS based Switches in Nanoscale"
    Mohammad Hossein Moaiyeri, Ali Jahanian, Keyvan Navi
    Nano-Micro Letters, Vol. 3, pp.178-188, 2011
  45. "Early buffer planning with congestion control using buffer requirement map"
    Ali Jahanian, Morteza Saheb zamani
    JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, Vol. 5, pp.949-973, 2010
  46. "Higher routability and reduced crosstalk noise by asynchronous multiplexing of on-chip interconnects"
    Ali Jahanian, Morteza Saheb zamani
    Scientia Iranica, Vol. 17, 2009
  47. "An Improved Standard Cell Placement Methodology using Hybrid Analytic and Heuristic Techniques"
    Ali Jahanian, ,
    ADVANCES IN COMPUTER SCIENCE AND ENGINEERING, Vol. 6, 2009
  48. "A Landmark-based Navigation System for High Speed Cars in the Roads with Branches"
    Mercedeh Sanjabi, Somayeh Maabi, Ali Jahanian,
    International Journal of Information Acquisition (IJIA), Vol. 6, pp.193-202, 2009
  49. "Using metro-on-chip in physical design flow for congestion and routability improvement"
    Ali Jahanian, Morteza Saheb zamani
    MICROELECTRONICS JOURNAL, Vol. 39, pp.261-274, 2008
  50. "Evaluating the Metro-on-Chip Methodology to Improve the Congestion and Routability"
    Ali Jahanian, Mostafa Rezvani, Morteza Saheb zamani, Mehrdad Najibi
    Advances in Computer and Information Sciences and Engineering, pp.689-696, 2008
  51. "Metro-on-Chip an efficient physical design technique for congestion reduction"
    Ali Jahanian, Morteza Saheb zamani
    IEICE ELECTRONICS EXPRESS (MSRT BLACKLIST), Vol. 4, pp.510-516, 2007
  52. "Evaluation prediction and reduction of routing congestion"
    Mahdi Saeedi, Ali Jahanian, Morteza Saheb zamani
    MICROELECTRONICS JOURNAL, Vol. 38, pp.942-958, 2007
  53. "قرنطینه سازی تروجانهای سخت افزاری در پردازنده های عام منظوره با روشهای نرم افزاری مبتنی بر مترجم"
    فرزانه قطب الدینی قاسم آباد، علی جهانیان
    علوم رایانش و فناوری اطلاعات، نسخه 17، صفحات:52-61، 1398
  54. "بررسی میزان بیان miRNA جهت تشخیص زودهنگام سرطان با استفاده از دروازه های منطقی DNA"
    طاهره یحیی، شهره زارع کاریزی، علی جهانیان
    دانشگاه علوم پزشکی اراک، نسخه 9، صفحات:96-109، 1395
  55. "طرح ریزی اتصالات امواج رادیویی روی مدارهای مجتمع خاص منظوره با هدف بهبود"
    زارعی علی محمد ، علی جهانیان
    the csi journal of computer science and engineering، نسخه 9، صفحات:34-41، 1389
  56. "توزیع مناسب منابع بافر با طرح ریزی بافرها در سطح جاسازی با هدف کاهش تعداد بافر و مدیریت تراکم"
    علی جهانیان، مرتضی صاحب الزمانی
    the csi journal of computer science and engineering، نسخه 5، صفحات:12-22، 1385

مقالات علمی ارائه شده در همایش‌ها

  1. "Protecting the FPGA IPs against Higher-order Side Channel Attacks using Dynamic Partial Reconfiguration"
    Ario Kianazad, Hamed Hossein talaee, Ali Jahanian
    2020 20th International Symposium on Computer Architecture and Digital Systems (CADS), pp.1-6, 2020
  2. "Real Vulnerabilities in Partial Reconfigurable Design Cycles; Case Study for Implementation of Hardware Security Modules"
    Hanieh Jafarzadeh, Ali Jahanian
    2020 20th International Symposium on Computer Architecture and Digital Systems (CADS), 2020
  3. "Vulnerability Analysis Against Fault Attack in terms of the Timing Behavior of Fault Injection"
    Mahbube Fakhire, Ali Jahanian
    2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp.374-379, 2020
  4. ""
    Farzaneh Ghobaddini ghasem abad, Ali Jahanian
    CSICC 2020, 2020
  5. "High Accuracy Multi-input DNA Logic Gate using the Spatially Localized DNA structures"
    Ehsan Jamalzadeh, Ali Jahanian
    CSICC 2020, 2020
  6. "Security Improvement of FPGA Design Against Timing Side Channel Attack Using Dynamic Delay Management"
    Bayat-Makou Pourya, Ali Jahanian, Reshadi Media
    IEEE Canadian Conference on Electrical Computer Engineering (CCECE), 2018
  7. "Efficient Mapping of DNA Logic Circuits on Parallelized Digital Microfluidic Architcture"
    Zohreh Beiki, Maryam Taajobian, Ali Jahanian
    19th International Symposium on Computer Architecture and Digital Systems (CADS), pp.93-98, 2017
  8. "Scalable Security Path Methodology A Cost-security Trade-off to Protect FPGA IPs against Active and Passive Tampers"
    SHARAREH ZAMANZADEH, Ali Jahanian
    Asian Hardware Oriented Security and Trust Symposium (AsianHOST), pp.85-90, 2017
  9. "High-Performance General-Purpose Arithmetic Operations using the Massive Parallel DNA-based Computation"
    Mercedeh Sanjabi, Ali Jahanian, Maryam Tahmasbi
    EuroMicro Digital System Design (DSD2017), pp.543-546, 2017
  10. "Layout Vulnerability Reduction against Trojan Insertion using Security-aware White Space Distribution"
    Hamed Hossein Talaee, Ali Jahanian
    International Symposium on VLSI (ISVLSI), pp.551-555, 2017
  11. "A new Cell Placement Algorithm for Localized DNA Logic Circuits Mounted on Origami Surface"
    Sedighe Farhadtoosky, Ali Jahanian
    International Conference on DNA Computing and Molecular Programming (DNA22), pp.102-104, 2016
  12. "Isolating the Register-bank Trojans in General-purpose Microprocessors using Secure Programming"
    Peyman Talebian, Ali Jahanian
    1st International Conference on New Research Achievements in Electrical and Computer Engineering, 2016
  13. ""
    Ali Jahanian
    1st International Conference on New Research Achievements in Electrical and Computer Engineering, pp.436-443, 2016
  14. "Fault-tolerant architecture and CAD algorithm for field-programmable pin-constrained digital microfluidic biochips"
    Alireza Abdoli, Ali Jahanian
    CSI Symposium on Real-Time and Embedded Systems and Technologies (RTEST), 2015
  15. ""
    SHARAREH ZAMANZADEH, Ali Jahanian
    12th International ISC conference on Information security and cryptology, 2015
  16. ""
    Bahareh Ahmadi Haji, Mehrshad Vosoughi, Ali Jahanian
    12th International ISC conference on Information security and cryptology, 2015
  17. "DENA a Configurable Architecture for Multi-stage DNA Logic Circuit Design"
    Zohreh Beiki, Ali Jahanian
    International Conference on DNA Computing and Molecular Programming (DNA21), pp.17-18, 2015
  18. "A General-Purpose Field-Programmable Pin-Constrained Digital Microfluidic Biochip"
    Ali Jahanian
    International Symposium on Computer Architecture and digital systems ( CADS ), 2013
  19. "RF resource planning in application specific integrated circuits to improve timing closure"
    Ali Jahanian
    International Symposium on Computer Architecture and digital systems ( CADS ), pp.131-132, 2013
  20. "Improved performance and resource usage of FPGA using resource-aware design the case of decimal array multiplier"
    Adel Hosseiny, Saba Amanollahi Baharvand, Ali Jahanian
    International Symposium on Computer Architecture and digital systems ( CADS ), pp.121-122, 2013
  21. ""
    SHARAREH ZAMANZADEH, Ali Jahanian
    21st IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), pp.52-53, 2013
  22. "RF-Interconnect resource assignment and placement algorithms in application specific ICs to improve performance and reduce routing congestion"
    Ali Jahanian, Bahareh Poorshirazi
    Euromicro conference on digital system design, 2012
  23. "EJOP an extensible Java processor with reasonable performance/flexibility trade-off"
    Ali Jahanian
    EuroMicro Digital System Design(DSD), pp.415-418, 2012
  24. "Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage"
    Marzieh Morshedzadeh, Ali Jahanian
    Great Lakes Symposium on VLSI (GLSVLSI)(2012), pp.303-306, 2012
  25. "Modeling evaluation and mitigation of SEU error in three-dimensional FPGAs"
    Ali Jahanian,
    International Symposium on Computer Architecture and Digital Systems (CADS), 2012
  26. "ParSA parallel simulated annealing placement algorithm for multi-core systems"
    Ali Jahanian, Saba Amanollahi Baharvand, Negar Niralaee
    International Symposium on Computer Architecture and Digital Systems (CADS), 2012
  27. "Improved performance and power consumption of three-dimensional FPGAs using Carbon Nanotube interconnects"
    Ali Jahanian
    International Symposium on Computer Architecture and Digital Systems (CADS), 2012
  28. "EduCAD an Efficient Flexible and Easily Revisable Physical Design Tool for Educational Purposes"
    Ali Jahanian, Saba Amanollahi Baharvand
    Design Automation and test(Date), 2012
  29. "Edu3 a simple and efficient platform for education of three-dimensional physical design automation algorithms"
    Ali Jahanian, Saba Amanollahi Baharvand
    Design Automation and test(Date), 2012
  30. "Landmark-based car navigation with overtake capability in multi-agent environments"
    Ali Jahanian,
    4th ICAART, 2012
  31. "VMAP a variation map-aware placement algorithm for leakage power reduction in FPGAs"
    Ali Jahanian
    14th euromicro conference on Digital System Design(DSD), 2011
  32. "A CNT/Metal Hybrid Routing Architecture to Improve Performance of Ultra-Large FPGAs"
    Ali Jahanian
    International Conference on Computer Design and Engineering (ICCDE) (2011 ), 2011
  33. "feasibility study of using the rf interconects in large fpgas to improve routing tracks usage"
    Ali Jahanian, Esfandiar Mehrshahi, Mohammad Taghi Teimoori
    2011IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, 2011
  34. "Congestion and Track Usage Improvement of Large FPGAs Using Metro-on-FPGA Methodology"
    Ali Jahanian
    Great Lakes Symposium on VLSI (GLSVLSI) (2011 ), pp.49-54, 2011
  35. "Chip master planning an efficient methodology to improve design closure and complexity management of ultra large chips"
    Ali Jahanian
    CSI Internationa Symposium on Computer Architecture and Digital Systems(CADS), 2010
  36. "A thermal-aware delay model for pass transistor in FPGA switch boxes"
    Ali Jahanian, Morteza Saheb zamani
    , 2010
  37. "A light - weght car navigation algorithm for high speed agents using wireless landmarks"
    Ali Jahanian,
    ICIA 2009 IEEE International Conference on Information and Automation, 2009
  38. "multi -domain clock skew scheduling - Aware register placementto optimize clock distribution network"
    Ali Jahanian,
    date (design automation test in europe, 2009
  39. "improved performance and yield whih chip master planingdesign methodology"
    Ali Jahanian,
    GLSVLSI, 2009
  40. "Improved timing closure by early buffer planning in floor-placement design flow"
    Ali Jahanian, Morteza Saheb zamani
    GLSVLSI, pp.558-563, 2009
  41. "Improved performance and yield with Chip Master planning design methodology"
    Ali Jahanian,
    Great Lakes Symposium on VLSI (GLSVLSI) (2009 ), 2009
  42. "Performance and timing yield enhancement using Highway-on-Chip Planning"
    Ali Jahanian
    EuroMicro Digital System Design(DSD), 2008
  43. "Performance improvement of physical retiming with shortcut insertion"
    Adel Dokhanchi, Mostafa Rezvani, Ali Jahanian, Morteza Saheb zamani
    IEEE computer society annual symposium on VLSI, pp.215-220, 2008
  44. "Multi-level buffer block planning and buffer insertion for large design circuits"
    Ali Jahanian, Morteza Saheb zamani
    IEEE computer society annual symposium on VLSI, pp.411-415, 2008
  45. "Using asynchronous serial transmission in physical design for congestion reduction"
    Ali Jahanian
    IEEE East-West Design and Test Conference, 2007
  46. "Prediction and reduction of routing congestion"
    Ali Jahanian
    International Symposium on Physical Design(ISPD), 2006
  47. "Efficient host-independent coprocessor architecture for speech coding algorithms"
    Ali Jahanian
    EuroMicro Digital System Design(DSD), 2005
  48. "An efficient congestion reduction algorithm based on contour plotting"
    Ali Jahanian
    International Conference on Microelectronics, 2005
  49. "Congestion prediction from metric definition to routing estimation"
    Ali Jahanian
    International Conference on Microelectronics, 2005
  50. "Area efficient low power and robust design for add-compare-select units"
    Ali Jahanian
    EuroMicro Digital System Design(DSD), 2004
  51. "Ant colony solution dynamic Steiner tree problem"
    علی نور الله، علی جهانیان، ادیبی پیمان ، هاشمی تشکری سید مهدی
    هفتمین کنفرانس انجمن کامپیوتر ایران،
  52. "ارائه یک روش نقاب گذاری ریزدانه جهت مقاوم سازی تراشه های خاص منظوره در برابر حملات کانال جانبی"
    وهاب صمدی بخارائی، علی جهانیان
    بیست و هفتمین کنفرانس بین المللی کامپیوتر، انجمن کامپیوتر ایران، 1400
  53. "Flexible and Automatable Microfluidic-based Architecture and CAD Algorithm for Implementation of Large DNA Digital Storage"
    مصطفی پوراسداله، مریم تعجبیان، علی جهانیان
    بیست و هفتمین کنفرانس بین المللی کامپیوتر، انجمن کامپیوتر ایران، 1400
  54. "OVR: a Practical Metric for Vulnerability Assessment of Digital Circuits against Side-channel Attacks"
    وهاب صمدی بخارائی، علی جهانیان
    سیزدهمین کنفرانس ملی فرماندهی و کنترل، 1400
  55. "Cost-Effective and Practical Countermeasure against the Template Side Channel Attack"
    فرشیده کردی، حامد حسین طلائی، علی جهانیان
    هفدهمین کنفرانس بین المللی انجمن رمز ایران، صفحات:54-60، 1399
  56. "Analysis of Geometrical Parameters for Remote Side-Channel Attacks on Multi-Tenant FPGAs"
    میلاد سلیمیان، علی جهانیان
    هفدهمین کنفرانس بین المللی انجمن رمز ایران، صفحات:21-29، 1399
  57. "A New Nano-scale Differential Logic Style for Power Analysis Attack"
    عبدی امید، علی جهانیان
    بیست و ششمین کنفرانس ملی مهندسی برق، 1397
  58. "تشخیص الگوی زیست نشانگرهای گسترش عفونت ویروسی هپاتیت C با استفاده از دروازه منطقی DNA"
    ملیکاسادات مسعود، علی جهانیان
    بیست و سومین کنفرانس ملی سالانه انجمن کامپیوتر ایران، 1396
  59. "Security Improvement of FPGA Configuration File Against the Reverse Engineering Attack"
    شهرام شهابی آهنگر کلایی، شراره زمان زاده، علی جهانیان
    سیزدهمین کنفرانس بین المللی انجمن رمز ایران، صفحات:101-105، 1395
  60. "Drug Discovery Evolution Using the Customized Digital Microfluidic Biochips"
    شادی ممتحن، مریم تعجبیان، علی جهانیان
    بیست و چهارمین کنفرانس مهندسی برق ایران، 1395
  61. "Design of CAD ASIP for JIT extensible processor Case study on PathFinder routing algorithm"
    سیدحسن دریانورد، محمد عشقی، علی جهانیان
    بیست و سومین کنفرانس مهندسی برق ایران، 1394
  62. "ارائه یک معماری برنامه پذیر جدید برای تراشه های زیستی ریز سیال دیجیتال"
    عباس حداد، تعجبیان مریم، علی جهانیان
    بیست و دومین کنفرانس مهندسی برق ایرانICEE2014، 1393
  63. "Design of CAD ASIP for JIT extensible processor case study on Simulated Annealing placer"
    علی جهانیان
    بیست و دومین کنفرانس مهندسی برق ایرانICEE2014، 1393
  64. "ارائه الگوریتم افراز موازی و پیاده سازی آن روی واحد پردازش گرافیکی"
    سیده عاطفه طاهری تاری، علی جهانیان
    بیست و دومین کنفرانس مهندسی برق ایرانICEE2014، 1393
  65. "ارائه یک کتابخانه صنعتی سلول های استاندارد براساس فناوری نانولوله های کربنی"
    محمد جرنگی، علی جهانیان، مهیا سام دلیری، محمدحسین معیری
    نوزدهمین کنفرانس ملی سالانه انجمن کامپیوتر ایران، صفحات:950-955، 1392
  66. "طرح ریزی اتصالات امواج رادیویی روی مدارهای مجتمع خاص منظوره با هدف بهبود کارایی"
    علی محمد زارعی، علی جهانیان
    هجدهمین کنفرانس ملی سالانه انجمن کامپیوتر ایران، 1391
  67. "جلوگیری از درج ویروس های سخت افزاری با ارائه یک معماری جدید برای درخت سیگنال ساعت"
    مهرشاد وثوقی، علی جهانیان
    هجدهمین کنفرانس ملی سالانه انجمن کامپیوتر ایران، 1391
  68. "A new nanowire-based FPGA to improve routing congestion and routability"
    آرش فرکیش، علی جهانیان
    سمینار الکترونیک و فرصت های فرارو ( دانشگاه صنعتی شریف )، 1391
  69. "Clock tree network using hybrid RF/metal clock routing"
    زهره محمدی ارفع، علی جهانیان
    سمینار الکترونیک و فرصت های فرارو ( دانشگاه صنعتی شریف )، 1391
  70. "TrueFlex A Flexible and Efficient Evaluation Platform for Networked Automotive Systems"
    سیدعلی مرعشی، علی جهانیان
    بیستمین کنفرانس مهندسی برق ایرانICEE2012، 1391
  71. "Redesigned CMOS (4 2) compressor for fast binary multipliers"
    پیشوایی عبدالرضا ، قاسم جابری پور، علی جهانیان
    بیستمین کنفرانس مهندسی برق ایرانICEE2012، 1391
  72. "ارائه ی معماری و دستورات سفارشی جدید برای سفارشی سازی معماری پردازنده ی جاوا با هدف بهبود کارایی این نوع پردازنده"
    ابوالقاسمی نیلوفر، طالبی سمانه، علی جهانیان، نوری حمید
    بیستمین کنفرانس مهندسی برق ایرانICEE2012، 1391
  73. "Design implementation and improvement of decimal parallel multiplier on ASIC and FPGA"
    امین ملک پور، ملک پور سعید، علی جهانیان
    بیستمین کنفرانس مهندسی برق ایرانICEE2012، 1391
  74. "طراحی کمپرسور (2 4 CMOS سریع بر پایه دروازه XOR سه ورودی"
    عبدالرضا پیشوایی، قاسم جابری پور، علی جهانیان
    هفدهمین کنفرانس ملی سالانه انجمن کامپیوتر ایران، صفحات:300-305، 1390
  75. "Buffer planning using the buffer requirement map with congestion control"
    علی جهانیان
    سیزدهمین کنفرانس بین المللی انجمن کامپیوتر ایران، 1386
  76. "Buffer insertion during placement with floorplanning information"
    علی جهانیان
    دوازدهمین کنفرانس بین المللی انجمن کامپیوتر ایران، 1385
  77. "A hybrid heuristically and mathematically approach for VLSI standard cell placement"
    علی جهانیان
    یازدهمین کنفرانس انجمن کامپیوتر ایران، 1384
  78. "Feasibility of using component based software formal verification by hardware formal verification tools"
    علی جهانیان
    یازدهمین کنفرانس انجمن کامپیوتر ایران، 1384
  79. "Using On-chip RF-Interconnects to Optimize Clock Distribution Network In 19th Iranian Conference on Electrical Engineering (ICEE)"
    علی جهانیان
    نوزدهمین کنفرانس بین المللی برق ایران، 1384
  80. "Parallelizing the PathFinder Global Routing Algorithm using Multi-core Systems"
    علی جهانیان
    نوزدهمین کنفرانس بین المللی برق ایران، 1384
  81. "Hardware-Software Co-Simulation"
    علی جهانیان
    چهارمین کنفرانس بین المللی سالانه انجمن کامپیوتر ایران، 1377
  82. "بهبود ساختار جعبه سوئیچ به منظور مقاوم سازی آرایه های دروازه ای برنامه پذیر در برابر مهندسی معکوس رشته بیتی"
    شهرام شهابی آهنگر کلایی، علی جهانیان
    کنفرانس مهندسی برق ایران، 1371